III–V nanoelectronics and related surface/interface issues

The conventional logic gate architecture is not suitable for high-density integration of quantum devices which are non-robust and extremely structure- and charge-sensitive. In this paper, our novel hexagonal binary-decision-diagram (BDD) quantum circuit approach for III–V nanoelectronics is reviewed and related critical surface/interface issues for high-density integration are discussed. First, the basic concept and actual implementation method of our approach are explained, giving examples of novel BDD quantum integrated circuits where nanowire networks are controlled by nanoscale Schottky wrap gates. For high-density integration, growth of embedded sub-10 nm III–V quantum wire networks by selective molecular beam epitaxy (MBE) on patterned substrates is described, including effects of atomic hydrogen irradiation and kinetic control of wire width. The key processing issue lies in understanding and control of nanostructure surfaces/interfaces. Behavior of nanoscale Schottky gates, recent scanning tunneling microscopy (STM)/scanning tunneling spectroscopy (STS) studies of surface states, and successful removal of surface states by MBE-grown silicon interface control layer are discussed.