(beta)-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed (beta)-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the (beta)-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. (beta)-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed (beta)-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of (beta)-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant (beta)-Helix interconnect will have a total standoff height of 110 (mu)m, radius of 37 (mu)m and cross section area of 525 (mu)m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the (beta)-Helix interconnect, especially when the interconnect density is high.