Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO2/HfSiO/SiO2 trilayer and HfTiSiO/SiO2 bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO2 underlayers degrades the EOT–Jg characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO2 capping for improving EOT–Jg characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10−2 A/cm2 for a TiO2/HfSiO/SiO2 trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.