Surface passivation of III–V semiconductors for future CMOS devices—Past research, present status and key issues for future

Currently, III–V metal–insulator–semiconductor field effect transistors (MISFETs) are considered to be promising device candidates for the so-called “More Moore Approach” to continue scaling CMOS transistors on the silicon platform. Strong interest also exists in III–V nanowire MISFETs as a possible candidate for a “Beyond CMOS”-type device. III–V sensors using insulator–semiconductor interfaces are good candidates for “More Moore”-type of devices on the Si platform. The success of these new approaches for future electronics depends on the availability of a surface passivation technology which can realize pinning-free, high-quality interfaces between insulator and III–V semiconductors. This paper reviews the past history, present status and key issues of the research on the surface passivation technology for III–V semiconductors. First, a brief survey of previous research on surface passivation and MISFETs is made, and Fermi level pinning at insulator–semiconductor interface is discussed. Then, a brief review is made on recent approaches of interface control for high-k III–V MIS structures. Subsequently, as an actual example of interface control, latest results on the authors’ surface passivation approach using a silicon interface control layer (Si ICL) are discussed. Finally, a photoluminescence (PL) method to characterize the interface quality is presented as an efficient contactless and non-destructive method which can be applied at each step of interface formation process without fabrication of MIS capacitors and MISFETs.