Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors

In this work, we present an approach towards improving a vertical field-effect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant diffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.