Abstract :
A bit-parallel systolic multiplier in the finite field GF(2/sup m/) over the polynomial basis, where irreducible trinomials x/sup m/ +x/sup n/+1 generate the fields GF(2/sup m/) is presented. The latency of the proposed multiplier requires only 2m-1 clock cycles. The architecture has the advantage of low latency, low circuit complexity and high throughput, as compared with traditional systolic multipliers. Moreover, the multiplier is highly regular, modular, and therefore, well-suited for VLSI implementation.
