Behavioural specifications allocation to minimise bit level waste of functional units

Conventional synthesis algorithms produce schedules balanced in the number of operations executed per cycle and allocate operations to functional units of their same type and width. In most implementations some hardware waste appears, because some functional units are not used in all clock cycles. This waste is even greater when multiple precision specifications, i.e. those formed by operations of different widths, are synthesised, because some bits of the results produced must be discarded in some cycles. The allocation algorithm proposed minimises this waste by increasing the reuse of hardware resources. It extracts, prior to the allocation, the common operative kernel of specification operations, and successively breaks down operations into sets of smaller ones such that functional units reuse is possible in other parts of the schedule. These transformations produce new operations whose types and widths may be different from the original ones. In consequence, some specification operations are finally executed over a set of functional units linked by some glue logic. Experimental results show that the implementations proposed by our algorithm need a considerably smaller area than those proposed by conventional allocation algorithms. Also, due to operation transformations, the type, number, and width of the hardware resources in the datapaths produced may be different from the type, number, and width of the specification operations and variables. Additionally, an analytical method to estimate the area potentially saved by our algorithm in comparison to conventional ones is developed