Author/Authors :
Behrouzian Nejad، Mohammad نويسنده Sama Technical and Vocational Training College, Islamic Azad University, Shoushtar Branch, Shoushtar, Iran , , Behrouzian Nejad، Ebrahim نويسنده Department of Computer, Shoushtar Branch, Islamic Azad University, Shoushtar, Iran , , Sayahi، Aref نويسنده Department of Computer Engineering, Soosangerd Branch, Islamic Azad University, Soosangerd, Iran , , Hashemi، Sayed Mohsen نويسنده Young Researchers and Elite Club, Mayboad Branch, Islamic Azad University, Mayboad, Iran , , Chaharlang، Javad نويسنده Department of Computer Engineering, Masjed Soleyman Branch, Islamic Azad University, Masjed Soleyman, Iran ,
Abstract :
Mapping and scheduling problems are important steps in the on-chip network design, which the goal is usually to optimize design and minimize power consumption and run time of an application. A good technique should be considered the design constraints. Indeed, the mapping quality varies with consideration of design constraints and optimization objectives such as minimizing energy consumption, communication delays. To improve performance of Network-on-Chip (NoC), many assignment algorithms are proposed to minimize the communication overhead and energy consumption. In this paper, we described the basic ideas of NoC architecture and review and analyse powerfully and efficient mapping and scheduling techniques, which proposed for NoC architecture. According to this problem that these techniques can have advantages and disadvantages, this paper focused on the review of these techniques. Review result of these techniques is described in the table form.
