Fundamental principles of modeling timing in hardware description languages

A fundamental property of digital hardware designs including VLSI designs is timing which underlies the occurrence of hardware activities and their relative ordering. In essence, timing constitutes the external manifestation of the causal relation between the relevant hardware activities. The constituent components of a hardware system are inherently concurrent and the relative time ordering of the hardware activities is critical to the correct functioning of complex hardware system. Hardware description languages (HDLs) are primarily developed for describing and simulating hardware systems faithfully and correctly and must, therefore, be capable of describing timing, accurately and precisely. This paper examines the fundamental nature of timing in hardware designs and develops, through reasoning, the basic principles of modeling timing in HDLs. This paper then traces the evolution of the key syntactic and semantic timing constructs in HDLs starting with CDL and up to the contemporary HDLs including ADLIB¯SABLE, Verilog HDL, and VHDL, and critically examines them from the perspective of the basic principles of modeling timing in HDLs. Classical HDLs including CDL are limited to synchronous digital designs. In the contemporary hardware description languages including ADLIB¯SABLE, CONLAN, Verilog, and VHDL, the timing models fail to encapsulate the true nature of hardware. While ADLIB and Verilog HDL fail to detect inconsistent events leading to the generation of potentially erroneous results, the concept of delta delay in VHDL which, in turn, is based on the BCL time model of CONLAN, suffers from a serious flaw.