The effect of thin film stress levels on CMP polish rates for PETEOS wafers

Chemical mechanical planarisation (CMP) is presently the process of choice for integrated circuit (IC) manufacturers when polishing inter-level oxide layers on silicon wafers to achieve global planarity. This paper will investigate the relationship between the deposited thin film stress levels and the removal rate across the wafer, which some literature maintains as being strongly linear. Experimental results will attempt to show that rather than it being a linear relationship, it is a relationship of the form:R=a ebσGiven that this relationship is substantially correct, then knowledge of the constants a and b will enable predictions of polishing rates to be made under various stress and pressure conditions. The relationship was modified by the addition of an asymptotic value for removal rate c, which improved the fit for the experimental data to the expression. From this, it is speculated that in future work, pad wear profiles could be developed through selective conditioning which would accommodate wafer bending so as to achieve a constant polishing rate over the whole wafer.