High voltage tolerant on-chip ESD protection in low-voltage BiCMOS process ☆

A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.