Wafer level backside emission microscopy: sample preparation

Emission microscopy has been widely adopted as an important tool for analyzing integrated circuit failures from the front surface. More recently, the development of multi-level metallization, flip-chip and lead-on-chip package designs either eliminated or greatly restricted this inspection avenue. An obvious alternative is to inspect from the backside of semiconductors. However, as silicon itself is a light-blocking material, thinning the back surface becomes essential to successful backside emission microscopy (EM). This paper describes a thinning and polishing technique enabling a user to locally thin a defective die on a wafer. This local thinning and polishing allows the wafer to retain its overall mechanical strength to survive the subsequent microprobing while providing a viewing window for EM analysis through the backside. © 1999 Elsevier Science Ltd. All rights reserved.