Bang-Bang Clock and Data Recovery Circuits – A Survey

Nowadays, the volume of the data transported in telecommunication systems is noticeably growing, which means the bandwidth required for data transmission is also increasing. However, due to the high transmission speed of data, those circuits are needed which can properly act at high speed (frequency). Clock and data recovery (CDR) circuits using bang-bang phase detector (BBPD) are widely used in communication systems mainly because of their high-frequency capabilities. However, bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, first, the architecture of BBCDR circuits is stated in addition to expressing the basic concepts of clock and data recovery circuits. Since the characteristics of frequency response of CDR are determined by jitter tolerance and jitter transfer characteristics, the concepts of these characteristics are mentioned and the presented analyses are evaluated.