Wave-mechanical study of gate tunneling leakage reduction in ultra-thin (<2 nm) dielectric MOS and H-MOS devices

The downsizing of the metal oxide semiconductor field effect transistor (MOSFET) to dimensions <0.1 μm in the next years requires the adoption of <2 nm thick gate oxides, which unfortunately give rise to a significant direct tunneling current. We apply in this paper a self-consistent one-dimensional Schrödinger–Poisson model to study MOSFET channel architectures likely to reduce this leakage. They consist in either increasing the insulator thickness using a larger permittivity nitride/oxide stack or burying the channel thanks to a tensile strained IV–IV heterostructure. It is shown that both solutions yield separately a reduction, and that the combination of these two strategies offers promising opportunities to fulfill ultimate complementary metal oxide semiconductor technology (≪0.1 μm) requirements regarding gate oxide downsizing.