Impact of high-permittivity dielectrics on speed performances and power consumption in double-gate-based CMOS circuits

The performances of double-gate (DG)-based CMOS circuits with high-κ dielectrics are analyzed in terms of inverter delay and static power consumption. We show that the use of a high-κ layer as gate dielectric degrades the short-channel immunity of DG devices and increases the power consumption, but for a gate dielectric relative permittivity κ lower than 50, the circuit performances still fill the ITRS requirements. Moreover, the use of a double gate dielectric layer (thin SiO2 oxide and high-κ layer) not only does not degrade the circuit performances, but even ameliorates the inverter speed. Finally, the analysis of back gate misalignment in DG circuits with double gate dielectric layer illustrates that the variation of the inverter performances induced by the back gate misalignment in these high-κ-based devices is comparable with that of the conventional (SiO2 oxide layer) structure.