Simulation study of circuit performances of independent double-gate (IDG) MOSFETs with high-permittivity gate dielectrics

This study analyzes by 2-D numerical simulation the electrical performances of independent double-gate (IDG) MOSFET with high-permittivity (high-κ) dielectric gate stacks. We particularly address the operation of elementary devices as well as of the associated CMOS inverters, which are investigated in terms of static power dissipation and delay. We show that the introduction of a pure high-κ gate dielectric layer degrades the device immunity to short-channel effects and the power consumption of the CMOS inverter, but simultaneously improves the inverter speed, with respect to performances of a reference transistor with a SiO2 gate oxide with the same equivalent oxide thickness. However, in real devices, the existence of a native oxide between the high-κ gate dielectric and the underlying semiconductor reduces parasitic electrostatic effects and sensibly improves inverter speed and power consumption. A detailed comparison between the operation of high-κ gate stack-based double-gate devices with independent and connected gates is also presented.