High Speed Reverse Converter for the Five Moduli Set {2n, 2n-1, 2n+1, 2n-3, 2n-1-1}

The new moduli set {2n, 2n-1, 2n+1, 2n-3, 2n-1-1} is profitable to construct high performance residue number system (RNS) due to well-formed moduli set and high dynamic range. Conversion from residues to binary is a bottleneck in RNS. With growth of number of moduli, this problem has been more critical due to complex multiplicative inverses. In this paper a high speed design of reverse converter for the moduli set {2n, 2n-1, 2n+1, 2n-3, 2n-1-1} is presented. This design is derived by using mix radix conversion (MRC) in three stages. Converter architecture is adder based which is suitable to realize efficient VLSI implementation. Proposed architecture has better delay performance compared to other reverse converters for five moduli sets in literature.