Performance issues in integrating temporality-based caching with prefetching

This work evaluates the performance effectiveness of combining two techniques for improving cache hit rate and reducing memory traffic in small on-chip direct-mapped caches. Temporality-based caching is an efficient technique for reducing unnecessary cache block conflicts in direct-mapped caches, but does not address compulsory misses. Tagged prefetching is a known technique for controlling compulsory misses, but has the potential for introducing high block interference, cache pollution and increased memory traffic in small direct-mapped caches. We propose and evaluate a group of caching strategies that integrate various combinations of temporality-based caching and tagged prefetching. Some combinations show both a remarkable improvement in hit rate and a substantial reduction in memory traffic.