An analytical performance model for multistage interconnection networks with finite, infinite and zero length buffers

Multistage Interconnection Networks (MINs) with crossbar switches have been used to interconnect processors and memory modules in parallel multiprocessor systems. They also play an increasingly important role in the development of Asynchronous Transfer Mode (ATM) networks. In this paper we analyze the general case of MINs, made of k × k switches with finite, infinite or zero length buffers (unbuffered). The exact solution of the steady-state distribution of the first stage is derived for all cases. We use this to get an approximation for the steady-state distributions in the second stage and beyond. In the case of unbuffered switches we reach the known exact solution for all the stages of the MIN. Our results are validated by extensive simulations.