Modeling and stability analysis of a simulation–stimulation interface for hardware-in-the-loop applications

This paper presents the stability evaluation of a Simulation–Stimulation (Sim–Stim) interface that integrates hardware to software to perform Hardware-In-the-Loop (HIL) studies for testing and developing electrical equipment. Modeling issues of such an interface are discussed and a practical Sim–Stim interface model whose parameters are sampling rate and time delay is developed for the theoretical evaluation of the stability. The developed Sim–Stim interface model is applied to a low power DC system and closed-loop stability of the resulting HIL system is studied analytically in terms of time delay and sampling rate. A prototype of Sim–Stim interface is designed and realized to validate theoretical stability results using HIL simulation.