Simulated fault injection methodology for gate-level quantum circuit reliability assessment

In quantum computation the importance of fault tolerance is paramount, due to the low reliability of the quantum circuit components. Therefore, several fault tolerance assessing tools and methodologies have been developed; most of them are analytic, dependent on the adopted fault model, and based on some simplifying assumptions. Simulation could have been a more realistic and accurate alternative had it not be confronted with the high complexity of simulating quantum circuits. However, a hardware description language (HDL) implementation for simulated fault injection (SFI) was proposed and tested for limited-size quantum circuits. This paper proposes a new, hybrid simulation-analytic, SFI-based methodology for quantum circuit fault tolerance assessment that is scalable to arbitrary size circuits. Each logical qubit from the quantum circuit is encoded by several physical qubits, and each logical gate can be decomposed into physical gates (acting on physical qubits). The HDL-based SFI evaluation result from the physical qubit level comes under the form of a failure rate, which is then fed to the analytical assessment process performed at the logical level. The analytical and simulation results prove the fact that, while maintaining a high accuracy of reliability assessment, this hybrid methodology can be applied to larger quantum circuits.