Hardware implementation of optical flow constraint equation using FPGAs

This paper describes the hardware implementation of a high complexity algorithm to estimate the optical flow from image sequences in real time. Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work, a specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hardware has many applications in fields like object recognition, image segmentation, autonomous navigation, and security systems. The final system has been developed with hardware that combines FPGA technology and discrete FIFO memories.