2× oversampling 2.5 Gbps clock and data recovery with phase picking method

A CMOS clock and data recovery circuit with 2× oversampling for multi-gigabit data rates is described. It uses multi-phase clocks and parallel sampling techniques to reduce the speed requirements. The circuit can generate 1:8 demultiplexed outputs or 1:1 serial output. The circuit adopts 2× oversampling technique and phase picking data recovery algorithm. Since the circuit oversamples twice per bit period (2×), the chip area and power consumption can be reduced compared to 3× or 4× algorithm. The proposed circuit was designed using TSMC 0.35 μm CMOS technology. Simulation results show that the circuit is capable of recovering clock and data at a speed of 2.5 Gbps and consuming 230 mW under 3.3 V power supply.