A CMOS bandgap reference voltage generator with reduced voltage variation and BJT area

This paper proposes a new bandgap reference (BGR) circuit which adopts a cascode current mirror biasing for reducing the reference voltage variation and a novel sizing method for reducing the PNP BJT area. The proposed BGR was designed and fabricated using 0.18 μm triple-well CMOS process which provides only normal VTH transistors. ference voltage variation of BGR was reduced from 0.5 mV (conventional) to 0.09 mV (proposed) using cascode current mirror biasing method. And the ratio of BJT emitter areas was reduced by a factor of 20 through the novel sizing method.