Optimization of JK Flip Flop Layout with Minimal Average Power of Consumption based on ACOR, Fuzzy-ACOR, GA, and Fuzzy-GA

The object of heuristic algorithms is to produce an optimum solution for solving a problem. When the number of variables in the problem is high the Heuristic Algorithms are used. In this article the goal is to find an optimum layout for JK Flip Flop for minimizing the average power. There are twenty MOSFETs with different channel widths. They make a twenty dimensional search space which are independent decision variables. Motivated by the convergence of Ant Colony Optimization in real domain (ACOR) and Genetic Algorithm (GA) and the link of MATLAB with HSPICE Software the optimized layout of JK Flip Flop is obtained. Based on ACOR, Fuzzy-ACOR, GA, Fuzzy-GA algorithms the best resulting JK Flip Flop layout in CMOS Technology with supply voltage of 5v has the average power consumption of 1.6 nW with Fuzzy-ACOR.