Architectural Strategies of Low Power VLSI Versatile Multimedia Functional Unit

Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major consideration, where power dissipation has become as important a consideration as performance and area. This paper reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The paper concludes with the future challenges that must be met to design low power, high performance systems. In the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power consideration was mostly of only secondary importance. In this paper we introduced the low power VLSI techniques in the architecture of VMFU. In this paper we implemented radix 4 algorithm and SPST technique in VMFU. The VMFU is a multiplexer controlled system. Multiple operations can be achieved by changing the selection bits of multiplexer. Approximately 30% of power can be reduced by using these low power VLSI techniques. The power estimation can be analysed with X-Power Analyser of XILINX tool and multiple operations can be simulated by using MODELSIM software.