Simulation of DA DCT Using ECAT for Reducing the Truncation Errors

Discrete cosine transform (DCT) is widely used in image and video compression applications. The paper mainly deals with implementation of image compression application based on Distributed Arithmetic (DA) DCT using Error Compensated Adder Tree (ECAT) and simulating it to achieve low error rate. Distributed Arithmetic (DA) based Error Compensated Adder Tree (ECAT) is operates shifting and addition in parallel instead of using multipliers where the complexity is reduced. The proposed architecture deals with 9 bit input and 12 bit output where it meets the Peak Signal to Noise Ratio (PSNR) requirements. Advantages of ECAT based DA-DCT are low error rate and improved speed in image and video compression applications. The project is implemented in Verilog HDL language and simulated in ModelSim XE III 6.4b. The project synthesis is done using Xilinx ISE 10.1. The results obtained were evaluated with the help of MATLAB