A VHDL Implementation of Direct, Pipelined and Distributed Arithmetic FIR Filters

Digital filters are typically used to modify or alter the attributes of a signal in the time or frequency domain. In this project, various FIR filter structures will be studied and implemented in VHDL. Basic arithmetic blocks to carry out DSP on FPGAs will be discussed. The very popular LUT based approach for arithmetic circuit implementation will be presented. The conventional PDSP MAC and Distributed arithmetic MAC units will be implemented and their performance will be compared. Usage of Pipelining in multipliers for improving the speed will also be discussed. The ModelSim XE simulator will be used to simulate the design at various stages. Xilinx synthesis tool (XST) will be used to synthesize the design for spartan3E family FPGA (XC3S500E). Xilinx Placement & Routing tools will be used for backend, design optimization and I/O routing