An advancement in the N×N Multiplier Architecture Realization via the Ancient Indian Vedic Mathematics

Multiplication is an crucial unfussy, basic function in arithmetic procedures and Vedic mathematics is a endowment prearranged for the paramount of human race, due to the capability it bestows for quicker intellectual computation. This paper presents the effectiveness of Urdhva Triyagbhyam Vedic technique for multiplication which cuffs a distinction in the authentic actual development of multiplication itself. It facilitates parallel generation of partial products and eradicates surplus, preventable multiplication steps. The anticipated N×N Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE Design Suite 13.1. The projected architecture is a N×N Vedic multiplier whilst the VHDL coding is done for 128×128 bit multiplication process. The result shows the efficiency in terms of area employment and rapidity