Adiabatic Improved Efficient Charge Recovery Logic for Low Power CMOS Logic

Abstract - Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from its switching activity, which is mainly influenced by the supply voltage and effective capacitance. The low-power requirements of present electronic systems have challenged the scientific research towards the study of technological, architectural and circuital solutions that allow a reduction of the energy dissipated by an electronic circuit. One of the main causes of energy dissipation in CMOS circuits is due to the charging and discharging of the node capacitances of the circuits, present both as a load and as parasitic. Such part of the total power dissipated by a circuit is called dynamic power. In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching technique is use. Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. The term adiabatic comes from thermodynamics, used to describe a process in which there is no exchange of heat with the environment. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. The adiabatic switching technique can achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. Power reduction is achieved by recovering the energy in the recover phase of the supply clock.