A Study of Built- in Self-test of RAMs

The task of testing a RAM chip to guarantee its functionality is extremely complex and often very time consuming. In addition to the problem of testing the RAM chips themselves, the incorporation of the chips into systems has caused test generation’s cost to grow exponentially. A widely accepted approach to deal with the testing problem at the chip level is to incorporate built- in self- test(BIST) capability inside a RAM chip. This increases the controllability and observability of the chip, thereby making the test generation and fault detection easier. In conventional testing, test patterns are generated externally by using computer- aided design (CAD) tools. The test patterns and the expected responses of the circuit under test to these test patterns are used by an automatic test equipment(ATE) to determine if the actual responses match the expected ones. On the other hand, in BIST, the test pattern generation and the output response evaluation are done on chip. Thus the use of expensive ATE machines to test chips can be avoided. In this paper, we present an overview of the types of BIST, and RAM functional fault models and various march tests for RAM as well as the advantages of BIST scheme.