Design and Analysis of Low power 6T SRAM Cell

Increasing area overhead is a major design concern in low-power sub-threshold SRAM designs, due to stability considerations. The extensive growth of battery operated devices has made low-power design important in recent years. As electronics are being integrated into portable devices, the demand grows for increased functionality, with reduced size and long battery life. This implies a need to balance ultra-low power with area-efficient design. An obvious way to minimize energy per operation is to decrease VDD. This decreases active power, as well as leakage power, which is affected by DIB. If VDD is decreased too sharply, however, increased delay time causes the power-delay product (PDP) to rise, can be kept minimum if operated in Sub-threshold region. In this paper the advantages of the sub-threshold inverter compared to the conventional strong inversion inverter with 90 nm technology in Cadence is presented. A one-Bit 6T SRAM, sense amplifier, and precharge circuit is designed using HSPICE 45nm technology.