The readout system of the H1 silicon detectors

The H1 detector at HERA at DESY presently undergoes a major upgrade. In this context silicon strip detectors have been installed at the beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 silicon detectors and performance data of the complete readout chain.