Title of article
The readout system of the H1 silicon detectors
Author/Authors
Bürger، نويسنده , , J. and Hansen، نويسنده , , K. and Lange، نويسنده , , David W. and Prell، نويسنده , , Stanislav S. and Zimmermann، نويسنده , , W. and Henschel، نويسنده , , H. Michael Klein، نويسنده , , M. and Kostka، نويسنده , , P. and Lange، نويسنده , , W. and Meiكner، نويسنده , , J. and Peppel، نويسنده , , E. and Sciacca، نويسنده , , G. and Stolze، نويسنده , , K. and Winde، نويسنده , , M. and Clarke، نويسنده , , D. and Haynes، نويسنده , , W.J. and Noyes، نويسنده , , G.W. and Jِnsson، نويسنده , , L. and Gabathuler، نويسنده , , K. and Horisberger، نويسنده , , Kathryn R. and Wagener، نويسنده , , M. and Eichler، نويسنده , , R. and Erdmann، نويسنده , , W. and Niggli، نويسنده , , H. and Pitzl، نويسنده , , D.، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 1995
Pages
6
From page
422
To page
427
Abstract
The H1 detector at HERA at DESY presently undergoes a major upgrade. In this context silicon strip detectors have been installed at the beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 silicon detectors and performance data of the complete readout chain.
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Serial Year
1995
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Record number
1996367
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