Author/Authors :
Ikeda، نويسنده , , Hirokazu and Saitoh، نويسنده , , Yutaka and Yamanaka، نويسنده , , Junko and Kitta، نويسنده , , Tatsuya، نويسنده ,
Abstract :
A single-channel CMOS preamplifier circuit was fabricated as a part of R&D efforts to design a 128-channel preamplifier chip for a silicon vertex detector of the BELLE collaboration. The prototype chip was evaluated in detail with special emphasis being placed on its analog circuit design and performance. An eight-stage digital/analog pipe-line, and a quadruple-correlated noise filter with a low-noise preamplifier circuit include key technologies for the design.