An area efficient 128 channel counter chip

A shift register of N bit length can be configured (for most N) with a single exclusive-OR gate to generate periodically 2N − 1 different states. As each state is directly related to the number of clock pulses received, such a circuit can be used as a counter. The sequential readout of the bit pattern requires nearly no additional logic and many “shift counters” can easily be daisy chained during readout in a multichannel system. A very regular and compact layout is possible due to the simple structure. The maximum clocking frequency of the circuit is high (above 50 MHz in a 2.4 μm process) and independent of the length. A 128 channel scaler chip has been designed and tested to be used in the Bonn Compton polarimeter for a fast measurement of beam profiles with silicon strip detectors. Other possible applications of this concept are specialized readout chips for microstrip and pixel detectors.