Position resolution and charge collection efficiency

The spatial resolution of silicon strip detectors is determined mainly by the detector layout. By optimising the strip layout one can achieve a significant improvement of the performance. The work presented here is a study of the influence of the detector layout on the position resolution and the charge collection efficiency for silicon detectors with a read out pitch of 200 μm. Fourteen different test structures have been designed and built. The structures vary in the number of intermediate strips and the width of the implant. On some structures a metal overlap is used to enhance the capacitive coupling between strips. The length and the width of the metal overlap are varied as well. All test structures have been studied in a test beam. In particular the position resolution and the charge transfer were examined. The outcome of this analysis is compared to the interstrip and backplane capacitances measured on these structures.