Design and Implementations of Linear Congruential Generator into FPGA

This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA. The circuit is derived from LCG algorithm proposed by Lehmer. Wordlengths reduction technique has been used to simplify the circuit. Several nets connection among the blocks of the circuit are ignored or disconnected. Simulation either behavior or timing have been done successfully. Four best Xilinx chips are chosen to gather comparison data of maximum speed and area occupied. Kintex 7 is the fastest chip among all it is about 309 MHz and Spartan 6 is slowest one which is only 73 MHz. The area occupied is similar among all of the selected chips.