Presentation of an Algorithm Configuration for Network-on-Chip Architecture with Reconfiguration Ability

Due to the challenge that the number of cores are combined on a single chip, the network on chip (NoC) has gradually become a popular solution. And recently, researchers have focused on improving the performance of NoC chips to achieve good performance. In this paper, we present an Algorithm Configuration for Network-on-Chip Architecture with reconfiguration ability for designing NoC with specific use. NoC architecture with reconfigurable capability reduces the complexity of the design and makes the layout of the NoC relatively more flexible compared to the layout of creating the topology map and the mapping design. Moreover, our Algorithm Configuration is for the optimized networks with better performance. NoC architecture with reconfigurable capability can be determined with a proper size for a specific purpose, and it can be configured according to the communication relation in order to ensure that the final system is optimized. A simulator with a proper cycle for imitating the three networks was deployed, and it was designed with our plan and two others methods for the same performance in the same environment. The results show that our system works efficiently.