Author/Authors :
Cappelli، نويسنده , , L. and Creti، نويسنده , , P. and Grancagnolo، نويسنده , , F. and Pepino، نويسنده , , A. and Tassielli، نويسنده , , G.، نويسنده ,
Abstract :
A fast readout algorithm for Cluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPGA board. The algorithm analyses and stores data coming from a Helium based drift tube instrumented by 1 GSPS fADC and represents the outcome of balancing between cluster identification efficiency and high speed performance. The algorithm can be implemented in electronics boards serving multiple fADC channels as an online preprocessing stage for drift chamber signals.
Keywords :
Cluster Counting/Timing , fADC , Drift chambers , Front-end electronics , FPGA
