Author/Authors :
Kim، نويسنده , , H.J. and Kim، نويسنده , , S.K. and LEE، نويسنده , , S.H and Hur، نويسنده , , T.W. and Kim، نويسنده , , C.H. and Wang، نويسنده , , F and Park، نويسنده , , I.C. and Kim، نويسنده , , Hee-Jong and Cheon، نويسنده , , B.G and Won، نويسنده , , E، نويسنده ,
Abstract :
We have developed a fast programmable trigger processor board based on a field programmable gate array and a complex programmable logic device for use in the BELLE experiment. The trigger board accommodates 144 ECL input signals, 2 NIM input signals, 24 ECL output signals, and the VME bus specification. An asynchronous trigger logic for counting isolated clusters is used. We have obtained a trigger latency of 50 ns with full access to input and output signals via a VME interface. The trigger logic can be modified at any time depending on the experimental conditions.
Keywords :
trigger , FPGA , CPLD , VME
