Low-noise design criteria for detector readout systems in deep submicron CMOS technology

This paper presents a study of the noise behavior of deep submicron CMOS transistors, in view of applications to analog front-end systems for high granularity detectors. The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/f noise contribution are investigated to find low-noise design criteria concerning the choice of the polarity and of the channel length of the preamplifier input device in low-power operating conditions. This analysis is supported by experimental data from noise measurements on CMOS devices belonging to a 0.35 μm process.