130 and 90 nm CMOS technologies for detector front-end applications

IC designers are moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 and 90 nm commercial processes are analyzed to provide an evaluation of the impact of technology scaling on the analog performances of a future generation of front-end chips. The behavior of 1/f and channel thermal noise parameters are studied to assess the effects of gate oxide quality and short-channel phenomena in CMOS processes with different gate oxide thickness and minimum channel length. The experimental analysis is focused on the design of low-power front-end circuits.