Front-end ASICs development for W–Si calorimeter at ILC (CALICE collaboration)

An ASIC (FLC_PHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten–silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e− with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLC_PHY4), to be tested extensively in test beam at CERN in autumn 2006. FLC_PHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out.