Application-specific architectures of CMOS monolithic active pixel sensors

Several development directions intended to adapt and optimize monolithic active pixel sensors for specific applications are presented in this work. The first example, compatible with the STAR microvertex upgrade, is based on a simple two-transistor pixel circuitry. It is suited for a long integration time, room-temperature operation and minimum power dissipation. In another approach for this application, a specific readout method is proposed, allowing optimization of the integration time independently of the full frame-readout time. The circuit consists of an in-pixel front-end voltage amplifier, with a gain on the order of five, followed by two analog memory cells. The extended version of this scheme, based on the implementation of more memory cells per pixel, is the solution considered for the outer layers of a microvertex detector at the international linear collider. For the two innermost layers, a circuit allowing fast frame scans together with on-line, on-chip data sparsification is proposed. The first results of this prototype demonstrate that the fixed pattern dispersion is reduced below a noise level of 15 e−, allowing the use of a single comparator or a low-resolution ADC per pixel column. A common element for most of the mentioned readout schemes is a low-noise, low power consumption, layout efficient in-pixel amplifier. A review of possible solutions for this element together with some experimental results is presented.