RISC & DSP System Application Design using VHDL.

The Reduced Instruction Set Computer (RISC) processor use fewer instructions with simple constructs, therefore they can be executed much faster within the CPU without having to use memory as often. It reduce execution time by simplifying the instruction set of the computer. The DSP processors are perform the operation such as Discrete Cosine transform (DCT), Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. This paper represent the design of a Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) system described using VHDL with both the single-cycle and pipelined processors and implement in a Field Programmable Logic Array FPGA). These days most microprocessor and microcontroller designs are based on Reduced Instruction Set Computer (RISC) core and many operation such as Discrete Cosine transform (DCT), Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. The goal of this work is to incorporate Digital Signal Processor (DSP) system operation in RISC processor.