Characterization of the polysilicon thin film transistors elaborated in high and low temperature processes. Study of the density of traps

The states density of traps (DOS) in the gap has been determined by a study of the temperature influence on the field-effect conductance of polycrystalline silicon thin film transistors fabricated in high and low temperature technologies. The effect on the DOS value of the granular structure, film thickness (between 50 and 150 nm) and technological process has been investigated. On the one hand, for thin film transistors (TFTs) fabricated in a high temperature process, we observed that, when the film thickness is greater than 50 nm, the DOS distribution has a ‘band tailing’ with an exponential shape. The slope increases when the thickness decreases. This indicates the enhancement of the disorder due to an important density of defects localized in the grain and or in the grain boundaries. Moreover, for thin films (tf = 50 nm), the DOS curve shows a characteristic hump which proves the presence of dangling bonds. They are localized at 0.35 eV above the top of the valence band. On the other hand, the effect of the low temperature process produces particularities on the TFT DOS. The classical doped drain (CDD) exhibits a high density of states with a classical distribution (band tailing with an exponential shape). However, the lightly doped drain (LDD) TFT DOS shows a hump localized at 0.4 eV below the bottom of the conduction band. The difference observed on the DOS distributions is related to the in situ doping level of the polysilicon-deposited thin films.