The end of the CMOS roadmap—new landscape beyond

Reduction of feature sizes for semiconductor devices continues according to Mooreʹs law in order to achieve higher integration densities, higher speed, lower power consumption and lower costs. The latest ITRS roadmap 99 describes in detail the target values for scaling of CMOS down to 35 nm in the year 2014, which is the mainstream technology for logic and memory. Many challenges have to be addressed for the CMOS nodes below 100 nm regarding lithography, metallisation, power dissipation, circuit design and also for the device, but this is more a performance issue than a limitation from basic physical laws. ore, novel architectures for MOSFETs are needed, to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. The 25-nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. Thus, it is predicted that CMOS will not end with todayʹs roadmap at 35 nm or even before, but will continue with non-bulk devices and fully depleted channels. Finally, these ultimate MOSFETs are compared with single electronics. Both have a similar device structure and seem to converge for nanometer channel length and width. But for circuit applications the small MOSFET operating with few electrons will be preferred, due to faster switching speed and less tolerances.