Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Due to the limitations in conventional complementary metal–oxide–semiconductor (CMOS) scaling technology in recent years, innovation in transistor structures and integration of novel materials has been a key to enhancing the performance of CMOS field-effect transistors (FETs) of past technology generations. Tremendous progress of high dielectric constant (high-k) gate stacks has been made in recent years and some of them have come into application in CMOS devices. However, many challenges remain, such as: (a) suitable permittivity, band gap and band alignment for dielectrics, on Si, (b) thermodynamic stability and interface engineering at both high-k/Si interface and metal/metal interface, (c) depletion effect, high gate resistance and its incompatibility with high-k for metal gate, and (d) low performance attributed to threshold voltage instability. Based on current progress and fundamental considerations, we review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research. Finally, this review concludes with perspectives towards the future gate stack technology and challenges in advanced CMOS devices.