Electrical properties of n-GaAs epilayers, FET and HEMT structures grown on LT-GaAs by MBE

We have investigated the dependence of the conductive layer width and Hall mobility in n-GaAs/LT-GaAs structures on the conditions of low temperature (LT) buffer growth and on annealing parameters. Both the conductive layer width, as determined from electrochemical C- V profiling, as well as the carrier mobility of the doped epilayer decrease as the LT-GaAs growth temperature is reduced and decrease with duration and temperature of annealing. This degradation is attributed to the outdiffusion of excess arsenic and the formation of arsenic precipitates in the n-GaAs epilayer and to the outdiffusion of point defects, as indicated by Photoluminescence observations. The use of AlxGa1 − xAs/GaAs superlattice and GaAs as intermediate layers between the LT buffer and the active layers in field effect transistor (FET) and high electron mobility transistor (HEMT) structures results in maintaining both carrier mobility and doping profile at conventional layer levels. The improvement is attributed to the suppression of excess As and point defect outdiffusion from the LT-GaAs to the active layer.