Assessment of layer structures for GaInP/GaAs-heterojunction bipolar transistors

GaAs-based heterojunction bipolar transistors (HBTs) are expected to take an increasing share of the currently expanding market for mobile communications products. The GaInP/GaAs-system offers advantages for device performance and fabrication in comparison with the already established AlGaAs/GaAs-system. However, HBT fabrication is still not mature technology. The main obstacle is the reproducible supply of high quality HBT epitaxial layer structures. An appropriate evaluation of the HBT layer structures is essential to successfully establish the epitaxial growth technology. The ratio of current gain to base sheet resistance is known to be one of the most meaningful figures of merit for the HBT. Therefore, the development of proper epitaxial growth procedures for HBT layer structures includes a device qualification. To the end of the evaluation of GalnP/GaAs-HBT layer structures we have established a fast HBT process that additionally provides windows for material analysis in different depths of the structure. The fundamental device performance and the wafer uniformity are assessed by dc parameter mapping of large area devices and conventional test structures. Several material diagnostic techniques were applied to assess layer properties. Some of the capabilities of these methods are discussed. Our fast HBT process has been instrumental in the development of GalnP/GaAs HBT layer structures at Epitaxial Products International. Current gain of 161 at the base sheet resistance of 273 Ω sq−1 with a standard deviation of the current gain across a 3 in. wafer of 1% proves that these GalnP/GaAs-HBT layer structures are comparable with currently available state-of-the-art AlGaAs/GaAs-HBT layer structures. Parts of the work were performed within the EC-project ESPRIT 21315 GAMMA.